1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements that comprise a high-k metal gate electrode structure formed in an early process stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a high number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, most of the integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for gate insulation layers that separate the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling, in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions, to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region since the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may typically be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide-based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide-based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher may be used, for instance in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, appropriate metal-containing materials may also have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials. To this end, appropriate metal-containing materials may be provided so as to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysilicon-based electrode materials, may be substantially avoided. The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence since, for instance, the adjustment of an appropriate work function for the transistors of different conductivity type and the fact that high-k dielectric materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like, may require appropriate strategies, for instance with respect to encapsulating the sensitive gate materials. Therefore, different approaches have been developed, such as providing the high-k dielectric material at an early manufacturing stage and processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein the typical electrode material polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and for providing a highly conductive electrode metal. While this approach may provide superior uniformity of the work function and thus of the threshold voltage of the transistors, since the actual adjustment of the work function may be accomplished after any high temperature processes, a complex process sequence for providing the different work function metals in combination with the electrode metal may be required.
In other very promising approaches, the sophisticated gate electrode structures may be formed in an early manufacturing stage, while the further processing may be based on a plurality of well-established process strategies. In this case, the high-k dielectric material and any metal species for adjusting the work function may be provided prior to or upon patterning the gate electrode stack, which may comprise well-established materials, such as silicon and silicon/germanium, thereby enabling the further processing on the basis of well-established process techniques. On the other hand, the gate electrode stack and in particular the sensitive high-k dielectric materials, in combination with any metal-containing cap layers, may remain reliably confined by appropriate materials throughout the entire processing of the semiconductor device.
Moreover, additional concepts for enhancing performance of transistors have been developed by providing one or more strain-inducing mechanisms in order to increase the charge carrier mobility in the channel regions of the various transistors. It is well known that charge carrier mobility in silicon may be efficiently increased by applying certain strain components, such as tensile and compressive strain for N-channel transistors and P-channel transistors, respectively, so that superior transistor performance may be obtained for an otherwise identical transistor configuration compared to non-strained silicon materials. For instance, efficient strain-inducing mechanisms may be implemented by incorporating a strained semiconductor material in the drain and source regions of transistors, for instance in the form of a silicon/germanium alloy, a silicon/carbon alloy and the like, wherein the lattice mismatch between the semiconductor alloy and the silicon base material may result in a tensile or compressive state, which in turn may induce a desired type of strain in the channel region of the transistor.
Although the approach of providing a sophisticated high-k metal gate electrode structure in an early manufacturing stage, possibly in combination with additional strain-inducing mechanisms, may have the potential of providing extremely powerful semiconductor devices, such as CPUs, storage devices, systems on a chip (SOC) and the like, conventional approaches may still suffer from process non-uniformities, as will be described with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, such as a silicon substrate, and a semiconductor layer 102, such as a silicon layer or a semiconductor material comprising a significant amount of silicon. The semiconductor layer 102 typically comprises isolation structures (not shown), which laterally delineate semiconductor regions or active regions 102A, 102B, which are to be understood as semiconductor regions in the layer 102 in which PN junctions for one or more transistors are to be formed. In the example shown, the active region 102A may correspond to an N-channel transistor 150A. On the other hand, the active region 102B may correspond to a P-channel transistor 150B. Furthermore, as previously discussed, the transistor 150B has implemented therein a strain-inducing mechanism on the basis of a strain-inducing semiconductor material 152, such as a silicon/germanium alloy, which is provided in a strained state and induces a compressive strain component in a channel region 151. Moreover, in the manufacturing stage shown in FIG. 1a, the transistor 150A comprises a gate electrode structure 160A including a gate dielectric material 161A in combination with a metal-containing cap material 162A. As explained above, the gate dielectric material 161A comprises a high-k dielectric material so as to impart an increased permittivity to the gate dielectric material 161A, which may be accomplished, for instance, on the basis of hafnium oxide and the like. It should be appreciated that the gate dielectric material 161A may comprise a dielectric base layer (not shown), such as a silicon dioxide-based material, on which a high-k dielectric material may be formed. Moreover, the gate dielectric material 161A and/or the conductive cap material 162A, which may comprise titanium nitride and the like, have incorporated therein an appropriate metal species, such as lanthanum and the like, in order to adjust an appropriate work function for the gate electrode structure 160A. Similarly, the transistor 150B comprises a gate electrode structure 160B including a gate dielectric material 161B in combination with a conductive cap material 162B. Also, in this case, the dielectric material 161B comprises a high-k dielectric material, while at least one of the layers 161B and 162B contains an appropriate metal species, such as aluminum and the like, in order to provide the desired work function of the gate electrode structure 160B. It should be appreciated that, additionally, the band gap of a portion of the channel region 151 adjacent to the gate dielectric material may have to be adapted with respect to the electronic characteristics of the layers 161B, 162B, which may, for instance, be accomplished by providing an appropriate crystalline channel material (not shown), for instance in the form of a silicon/germanium alloy. Furthermore, the gate electrode structures 160A, 160B comprise a silicon material 163 followed by a dielectric cap material 164, which is substantially comprised of silicon nitride. Additionally, a sidewall spacer structure 165 is provided so as to laterally confine the materials 161A, 162A, 161B, 162B and 163 when forming the strain-inducing semiconductor material 152 and also during the further processing, as otherwise a significant variation of transistor characteristics may be caused upon modifying the materials 161A, 162A, 161B, 162B during the further processing. For example, the spacer structure 165 comprises a silicon nitride liner 165L in combination with a silicon nitride spacer 165S.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. The active regions 102A, 102B may be formed by providing isolation structures on the basis of well-established process strategies, thereby defining the lateral position and size of the active regions 102A, 102B. The basic doping of these regions is then established by using appropriate masking regimes in combination with implantation processes. Next, an appropriate dielectric material, such as silicon oxynitride in combination with a high-k dielectric material, may be deposited by using any appropriate deposition technique, possibly in combination with oxidation processes and the like. Thereafter, any appropriate process sequence may be applied for providing the layers 162A, 162B so as to achieve the desired work function for the gate electrode structures 160A, 160B. For example, appropriate material layers including the metal species may be deposited selectively above the regions 102A and 102B, respectively, and thereafter a diffusion may be initiated so as to drive the work function adjusting species into at least a portion of the previously provided dielectric material, thereby forming the layers 161A, 161B. Thereafter, the diffusion layers may be replaced by any appropriate metal-containing material, such as titanium nitride. In other cases, appropriate metal layer stacks may be formed above the gate dielectric materials so as to achieve the desired electronic characteristics. Next, the silicon material 163 is deposited in combination with the silicon nitride material of the cap layer 164, wherein additional materials may also be provided, such as hard mask materials and the like, as is required for patterning the resulting gate layer stack. After applying complex lithography and etch techniques for patterning the previously formed material layers, a silicon nitride liner material is deposited, for instance, by applying multilayer deposition techniques, which may then be patterned on the basis of plasma assisted etch recipes in order to obtain the liner 165L. Thereafter, a further silicon nitride material is deposited, for instance by low pressure chemical vapor deposition (LPCVD) and may be patterned into the spacer elements 165S. In other cases, the materials for the liner 165L and the spacer 165S may be deposited in subsequent deposition processes and may commonly be patterned. Typically, a width of the spacer structure 165 is selected so as to obtain a desired lateral offset of the strain-inducing semi-conductor material 152, since a reduced lateral offset from the channel region 151 results in an increased strain component, which in turn provides superior transistor performance. For example, a width of the spacer structure 165 may be approximately 10-13 nm, wherein a further reduction of spacer width may not be compatible with the further processing of the semiconductor device 100, in particular with the removal of the dielectric cap layer 164 in a later manufacturing stage.
In some approaches, the corresponding materials of the spacer structures 165 may be selectively patterned into the spacer structure 165 for the transistor 150B, whereas the spacer layer is preserved in the transistor 150A, thereby acting as a growth mask during the further processing. For this purpose, the resist mask may be formed so as to cover the transistor 150A having formed thereon the material layers for the spacer structure 165, while the transistor 150B is exposed to a reactive etch ambient in order to form the spacer structure 165 and further etch into the active region 102B, thereby forming recesses therein. Thereafter, the resist material is removed and the further processing is continued by performing a selective epitaxial growth process in order to deposit the strain-inducing semiconductor material 152, wherein the spacer layer still present above the transistor 150A and the spacer structure 165 in combination with the dielectric cap layer 164 in the gate electrode structure 160B act as an efficient mask material. Thereafter, the spacer layer above the transistor 150A is selectively etched so as to form the spacer structure 165 of the gate electrode structure 160A. In other strategies, a dedicated hard mask material may be provided selectively in the transistor 150A after patterning the spacer structures 165 in both transistors 150A, 150B.
FIG. 1b schematically illustrates the semiconductor device 100 when exposed to an etch process 104 for removing the cap layers 164 from the gate electrode structures 160A, 160B. As previously indicated, since a reduced width of the spacer structure 165 may be considered advantageous in view of reducing the lateral offset of the strain-inducing semi-conductor material 152, a certain probability may exist in unduly removing material of the spacer structure 165, thereby possibly exposing the sensitive materials 161A, 162A, 161B, 162B, which may result in a significant variation of the overall transistor characteristics. A corresponding undue material removal may occur on the basis of well-established wet chemical etch recipes for removing silicon nitride material by using, for instance, hot phosphoric acid. For this reason, plasma assisted etch recipes have been developed so as to reduce the lateral etch rate during the process 104, wherein, however, it has been observed that, for a spacer width of approximately 10-13 nm, nevertheless, significant material erosion in the spacer structure 164 may occur, thereby contributing to unacceptable device variabilities. Consequently, upon further device scaling, which may also require an enhancement of the strain-inducing mechanism, the conventional process strategy may result in significant yield losses.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.